The present invention relates generally to the fabrication of integrated circuits (IC""s), and more particularly to the fabrication of memory IC""s.
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and a common type of semiconductor memory is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells arranged in an array, with each cell adapted to store one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
DRAM storage capacitors are typically formed by etching deep trenches in a semiconductor substrate, and depositing and patterning a plurality of layers of conductive and insulating materials in order to produce storage capacitors that are adapted to store data, represented by a one or zero. Prior art planar DRAM designs typically comprise access FETs disposed in a subsequently deposited layer, disposed above and to the side of the storage capacitors.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products. More recent DRAM designs involve disposing the access FET directly above the storage capacitor, a design that is often referred to as a vertical DRAM, which saves space and results in the ability to place more DRAM cells on a single chip.
Both the array of DRAM cells and support devices for the DRAM cells such as logic circuits, gates, junctions, decoders, and drivers, as examples, are planar in a planar DRAM. In planar DRAM technology, isolation trenches (IT) are formed, a gate oxide is formed over the memory cells, and planar support devices are formed. The wafer is subjected to a number of wet etch processes that potentially may affect the isolation trench height after planarization. However, because these etch processes are well controlled, the isolation trench height is not impacted due to exposure to the etch processes after isolation trench planarization.
In vertical DRAM technology, support devices are typically disposed in one or more support regions that are separate from the vertical DRAM cell array region. Isolation trenches are disposed between individual DRAM cells and the various support devices in order to electrically isolate the memory cells and support devices, respectively, from one another. A vertical access FET is disposed over each DRAM cell. Then, an array top oxide (ATO) layer is disposed over the array region to form a vertical isolation layer for the array region while the support logic devices are being formed in the support region and vertical access FETs are being wired to the logic devices.
Whereas in planar vertical DRAM technology, isolation trench height after planarization is not substantially impacted by subsequent etch processes, in vertical DRAM manufacturing, a second planarization step is required after the isolation trench planarization in order to planarize the ATO. The vertical DRAM ATO planarization process is much more difficult to control, and contains more process steps, for example, often decreasing the isolation trench height and causing a variation in the height of the isolation trenches of the vertical DRAM device.
In vertical DRAM manufacturing, it is desirable to maintain the height of the isolation trenches in the support device region during the processing of the array region.
Embodiments of the present invention achieve technical advantages as a method of controlling the height of isolating trenches of a vertical DRAM using a support liner. The support liner preserves the isolation trench height and height variation of the vertical DRAM during the manufacturing process.
In one embodiment, a method of processing a semiconductor wafer is disclosed. The wafer has at least one array region and at least one support region, the array region including a plurality of vertical DRAM cells and the support region including a region reserved for support circuitry for the vertical DRAM cells. The array and support regions include a plurality of isolation trenches formed therein, and the wafer includes a pad nitride disposed thereon. The method includes disposing a support liner over the wafer support region, disposing a first insulating layer over the wafer, and planarizing the wafer to remove the first insulating layer from at least the support region and leave a portion of the first insulating layer in the array region. The support liner in the wafer support region protects the isolation trench top surface during the planarization of the wafer.
Also disclosed is a method of manufacturing a vertical DRAM device, including providing a semiconductor wafer comprising a workpiece, the workpiece including at least one array region and at least one support region, forming a pad nitride over the workpiece, and forming a plurality of vertical DRAM cells in the at least one array region of the workpiece. The method includes forming a plurality of isolation trenches in the array region and the support region, disposing a support liner over the workpiece, removing the support liner from the workpiece array region and disposing a first insulating layer over the workpiece. The first insulating layer is removed from a top surface of the workpiece, leaving a portion of the first insulating layer disposed over at least the array region.
Advantages of embodiments of the invention include providing a method of manufacturing vertical DRAM structure having isolation trenches with a well-controlled height within support regions of the wafer. The support liner protects the isolation trenches in the support region during the processing of the array region of the wafer. The original isolation trench height after planarization of the isolation trenches may be preserved through the array top oxide deposition and planarization processes. Height variation of isolation trenches across the surface of the wafer is also well-controlled in accordance with embodiments of the present invention.